Cache Memory, Memory mapping

Cache Memory, Memory mapping

Cache memory is a small, fast memory located close to the CPU, used to store frequently accessed data for quick retrieval.

Main memory (RAM) is larger and slower, used to store data and programs currently being processed.

Cache Memory, Memory mapping

1. Secondary Memory (SM) and Main Memory (MM)

• Pages (SM): Fixed-size blocks in secondary memory.
• Frames (MM): Fixed-size blocks in main memory.
• Page size in SM equals frame size in MM for efficient mapping.

2. Cache Memory

• Divided into smaller, independent cache blocks (lines).
• Blocks from MM are loaded into cache lines based on demand.

OS Role

• The operating system manages the subdivision of process pages and their loading into main memory.

Memory mapping

Memory mapping refers to:

1. Translating virtual addresses to physical addresses (as mentioned before).
2. The communication between main memory (MM) and cache memory, using blocks (cache) and words (MM).

Allowing programs to access hardware resources or memory regions efficiently.

Word Definition; The smallest addressable unit of memory; in byte-addressable memory, 1 word equals 1 byte.

Memory Configuration Conceptual:

• Main Memory Size: 64 words
• Block Size: 4 words
• Total Blocks: 64 / 4 =16 blocks

Block Numbering:

• Blocks are numbered from 0 to 15.

Memory Word Addressing:

• Memory words range from 0 to 63.
• Each block contains 4 words.
• 1 bit can indeed contain either 0 or 1 and is typically referred to as a memory cell.
• A memory cell is made up of transistors and capacitors in dynamic random-access memory (DRAM) technology. The capacitor holds the charge (representing a bit), and the transistor acts as a switch to control access to the capacitor.

Bits Required for Addressing:

• To address locations:
• 1 bit: 2 locations (0, 1)
• 2 bits: 4 locations (00, 01, 10, 11)
• 3 bits: 8 locations (000 to 111)

One bit can address two possible locations. Each bit’s two states (0 and 1) correspond to two distinct memory locations

To address 64 words: log⁡2(64)=6 bits required.

Hit Latency & Cache Miss

• Hit Latency: The time it takes for the CPU (processor) to check if data is in cache (using a specific tag data structure).
• Cache Miss: When data isn’t in the cache, requiring retrieval from slower main memory, increasing access time.